1. Field
Apparatuses consistent with example embodiments relate to a semiconductor circuit, and more particularly, to a semiconductor memory including pads arranged in parallel.
2. Description of Related Art
A semiconductor memory is manufactured through a plurality of processes. The plurality of manufacturing processes include processes of depositing or etching insulating materials, conductive materials, or semiconductor materials. When a die of the semiconductor memory is completely manufactured, inner pads, outer pads, and backend interconnection wires are exposed on a backend of the semiconductor memory.
The inner pads are connected with various elements manufactured inside the die of the semiconductor memory. The positions of the inner pads may be determined depending on the arrangement or configuration of the elements inside the die of the semiconductor memory. The outer pads are formed at positions that are easily connected with a semiconductor package surrounding the die of the semiconductor memory through interconnection wires.
The backend interconnection wires interconnect the inner pads and the outer pads. The backend interconnection wires are called a redistribution layer (RDL) in that the backend interconnection wires redistribute the positions of pads (that is, the inner pads) of the die of the semiconductor memory (to the positions of the outer pads).
With an increase in the length of the backed interconnection wires, power consumed by the backend interconnection wires may be increased, and signal integrity (SI) of signals transmitted through the backend interconnection wires may be reduced. Accordingly, studies on reducing the length of backend interconnection wires are consistently conducted.